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Llama2 70B (offline AI) Says stuff about the CPU scheduler Cores and ISA and I don't know how else to verify (is CPU core ISA determined by microcode and how to hack)
  • Similarly, Linux kernel developers have added support for asymmetric instruction availability in their schedulers through features like “CPU microcode updates”, which allow the OS to query a processor’s available instructions sets at runtime and make more informed decisions about thread placement as a result.

    This is bullshit, the microcode is not in any way a mechanism to query any information. It's an opaque blob provided by Intel and the system firmware. What's happening with Alder Lake is that AVX-512 is disabled through microcode, but if you're not Intel or a motherboard manufacturer, there is nothing you can do about that.

    If your goal is to make AVX-512 usable on your computer, don't bother with it. It will not magically make things go faster.

  • InitialsDiceBearhttps://github.com/dicebear/dicebearhttps://creativecommons.org/publicdomain/zero/1.0/„Initials” (https://github.com/dicebear/dicebear) by „DiceBear”, licensed under „CC0 1.0” (https://creativecommons.org/publicdomain/zero/1.0/)LU
    luchs @feddit.de
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